M68KMASM/D7 JULY 1983 M68000 FAMILY RESIDENT STRUCTURED ASSEMBLER REFERENCE MANUAL The information in this document has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, Motorola reserves the right to make changes to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights or the rights of others. EXORmacs, SYMbug, VERSAdos, VERSAmodule, VMC 68/2, VME/10 and VMEmodule are trademarks of Motorola Inc. This edition incorporates the information in any addendums to previous releases of this manual. Seventh Edition Copyright 1983 by Motorola Inc. Sixth Edition June 1983 ******************************************************************************** TABLE OF CONTENTS Page ---- CHAPTER 1 GENERAL INFORMATION 1.1 SCOPE .................................................... 1-1 1.2 INTRODUCTION ............................................. 1-1 1.3 M68000 FAMILY ASSEMBLY LANGUAGE .......................... 1-1 1.3.1 Machine-instruction Operation Codes .................... 1-2 1.3.2 Directives ............................................. 1-2 1.4 M68000 FAMILY RESIDENT STRUCTURED ASSEMBLER .............. 1-2 1.4.1 Assembler Purposes ..................................... 1-2 1.4.2 Assembler Processing ................................... 1-2 1.4.3 Microprocessor Types ................................... 1-3 1.5 RELOCATION AND LINKAGE ................................... 1-3 1.6 LINKER RESTRICTIONS ...................................... 1-4 1.7 NOTATION ................................................. 1-4 1.8 RELATED PUBLICATIONS ..................................... 1-4 CHAPTER 2 SOURCE PROGRAM CODING 2.1 INTRODUCTION ............................................. 2-1 2.2 COMMENTS ................................................. 2-1 2.3 EXECUTABLE INSTRUCTION FORMAT ............................ 2-1 2.4 SOURCE LINE FORMAT ....................................... 2-2 2.4.1 Label Field ............................................ 2-2 2.4.2 Operation Field ........................................ 2-2 2.4.3 Operand Field .......................................... 2-3 2.4.4 Comment Field .......................................... 2-3 2.5 INSTRUCTION MNEMONICS .................................... 2-4 2.5.1 Arithmetic Operations .................................. 2-4 2.5.2 MOVE Instruction ....................................... 2-4 2.5.3 Compare and Check Instructions ......................... 2-4 2.5.4 Logical Operations ..................................... 2-5 2.5.5 Shift Operations ....................................... 2-5 2.5.6 Bit Operations ......................................... 2-6 2.5.7 Conditional Operations ................................. 2-6 2.5.8 Branch Operations ...................................... 2-6 2.5.9 Jump Operations ........................................ 2-7 2.5.10 DBcc Instruction ....................................... 2-8 2.5.11 Load/Store Multiple Registers .......................... 2-8 2.5.12 Load Effective Address ................................. 2-9 2.5.13 Move to/from Control Register .......................... 2-10 2.5.14 Move to/from Address Space ............................. 2-10 2.6 SYMBOLS AND EXPRESSIONS .................................. 2-11 2.6.1 Symbols ................................................ 2-11 2.6.2 Symbol Definition Classes .............................. 2-12 2.6.3 User-Defined Labels .................................... 2-12 2.6.4 Expressions ............................................ 2-13 2.6.5 Operator Precedence .................................... 2-14 2.7 REGISTERS ................................................ 2-15 2.8 VARIANTS ON INSTRUCTION TYPES ............................ 2-16 2.9 ADDRESSING MODES ......................................... 2-18 2.9.1 Register Direct Modes .................................. 2-21 2.9.2 Memory Address ......................................... 2-21 2.9.2.1 Address Register Indirect ............................ 2-21 i ******************************************************************************** TABLE OF CONTENTS (cont'd) Page ---- 2.9.2.2 Address Register Indirect with Postincrement ......... 2-21 2.9.2.3 Address Register Indirect with Predecrement .......... 2-22 2.9.2.4 Address Register Indirect with Displacement .......... 2-22 2.9.2.5 Address Register Indirect with Index ................. 2-22 2.9.3 Special Address Modes ................................ 2-23 2.9.3.1 Absolute Short Address ............................... 2-23 2.9.3.2 Absolute Long Address ................................ 2-23 2.9.3.3 Program Counter with Displacement .................... 2-23 2.9.3.4 Program Counter with Index ........................... 2-24 2.9.3.5 Immediate Data ....................................... 2-24 2.10 NOTES ON ADDRESSING OPTIONS .............................. 2-24 CHAPTER 3 ASSEMBLER DIRECTIVES 3.1 INTRODUCTION ............................................. 3-1 3.2 ASSEMBLY CONTROL ......................................... 3-2 3.2.1 ORG - Absolute Origin .................................. 3-2 3.2.2 SECTION - Relocatable Program Section .................. 3-3 3.2.3 END - Program End ...................................... 3-3 3.2.4 OFFSET - Define Offsets ................................ 3-3 3.2.5 MASK2 - Assemble for MASK2 (MC68000 only) .............. 3-4 3.2.6 INCLUDE - Include Secondary File ....................... 3-4 3.3 SYMBOL DEFINITION ........................................ 3-4 3.3.1 EQU - Equate Symbol Value .............................. 3-4 3.3.2 SET - Set Symbol Value ................................. 3-4 3.3.3 REG - Define Register List ............................. 3-5 3.4 DATA DEFINITION/STORAGE ALLOCATION ....................... 3-5 3.4.1 DC - Define Constant ................................... 3-5 3.4.1.1 Examples of ASCII Strings ............................ 3-6 3.4.1.2 Examples of Numeric Constants ........................ 3-6 3.4.2 DS - Define Storage .................................... 3-7 3.4.3 DCB - Define Constant Block ............................ 3-7 3.4.4 COMLINE - Command Line ................................. 3-7 3.5 LISTING CONTROL .......................................... 3-8 3.5.1 PAGE - Top of Page ..................................... 3-8 3.5.2 Listing Output Options ................................. 3-8 3.5.2.1 LIST - List The Assembly ............................. 3-8 3.5.2.2 NOLIST - Do Not List The Assembly .................... 3-8 3.5.2.3 FORMAT - Format The Source Listing ................... 3-8 3.5.2.4 NOFORMAT - Do Not Format The Source Listing .......... 3-8 3.5.2.5 SPC - Space Between Source Lines ..................... 3-8 3.5.2.6 NOPAGE - Do Not Page Source Output ................... 3-9 3.5.2.7 LLEN - Line Length ................................... 3-9 3.5.2.8 TTL - Title .......................................... 3-9 3.5.2.9 NOOBJ - No Object .................................... 3-9 3.5.2.10 OPT - Assembler Output Options ....................... 3-9 3.6 FAIL - PROGRAMMER GENERATED ERROR ........................ 3-11 3.7 LINKAGE EDITOR CONTROL ................................... 3-11 3.7.1 IDNT - Relocatable Identification Record ............... 3-11 3.7.2 XDEF - External Symbol Definition ...................... 3-11 3.7.3 XREF - External Symbol Reference ....................... 3-11 ii ******************************************************************************** TABLE OF CONTENTS (cont'd) Page ---- CHAPTER 4 INVOKING THE ASSEMBLER 4.1 COMMAND LINE FORMAT ...................................... 4-1 4.1.1 Symbol Table Size Option ............................... 4-2 4.1.2 Microprocessor Type Option ............................. 4-2 4.2 ASSEMBLER OUTPUT ......................................... 4-2 4.3 ASSEMBLER RUNTIME ERRORS ................................. 4-3 CHAPTER 5 MACRO OPERATIONS AND CONDITIONAL ASSEMBLY 5.1 INTRODUCTION ............................................. 5-1 5.2 MACRO OPERATIONS ......................................... 5-1 5.2.1 Macro Definition ....................................... 5-2 5.2.2 Macro Invocation ....................................... 5-2 5.2.3 Macro Parameter Definition and Use ..................... 5-2 5.2.4 Labels within Macros ................................... 5-3 5.2.5 The MEXIT Directive .................................... 5-4 5.2.6 NARG Symbol ............................................ 5-4 5.2.7 Implementation of Macro Definition ..................... 5-5 5.2.8 Implementation of Macro Expansion ...................... 5-6 5.3 CONDITIONAL ASSEMBLY ..................................... 5-7 5.3.1 Conditional Assembly Structure ......................... 5-7 5.3.2 Example of Macro and Conditional Assembly Usage ........ 5-8 CHAPTER 6 STRUCTURED CONTROL STATEMENTS 6.1 INTRODUCTION ............................................. 6-1 6.2 KEYWORD SYMBOLS .......................................... 6-1 6.3 SYNTAX ................................................... 6-1 6.3.1 IF Statement ........................................... 6-3 6.3.2 FOR Statement .......................................... 6-3 6.3.3 REPEAT Statement ....................................... 6-4 6.3.4 WHILE Statement ........................................ 6-4 6.4 SIMPLE AND COMPOUND EXPRESSIONS ........................ 6-5 6.4.1 Simple Expressions ..................................... 6-5 6.4.1.1 Condition Code Expressions ........................... 6-5 6.4.1.2 Operand Comparison Expressions ....................... 6-6 6.4.2 Compound Expressions ................................... 6-7 6.5 SOURCE LINE FORMATTING ................................... 6-8 6.5.1 Class 1 Symbol Usage ................................... 6-8 6.5.2 Limited Free-Formatting ................................ 6-8 6.5.3 Nesting of Structured Statements ....................... 6-9 6.5.4 Assembly Listing Format ................................ 6-9 6.6 EFFECTS ON THE USER'S ENVIRONMENT ........................ 6-9 CHAPTER 7 GENERATING POSITION INDEPENDENT CODE 7.1 FORCING POSITION INDEPENDENCE ............................ 7-1 7.2 BASE-DISPLACEMENT ADDRESSING ............................. 7-1 7.3 BASE-DISPLACEMENT IN CONJUNCTION WITH FORCED POSITION INDEPENDENCE ........................................... 7-2 iii ******************************************************************************** TABLE OF CONTENTS (cont'd) Page ---- APPENDIX A INSTRUCTION SET SUMMARY .................................. A-1 APPENDIX B CHARACTER SET ............................................ B-1 APPENDIX C SAMPLE ASSEMBLER OUTPUT .................................. C-1 APPENDIX D EXAMPLE OF LINKED ASSEMBLY-LANGUAGE PROGRAMS ............. D-1 APPENDIX E ASSEMBLY ERROR CODES ..................................... E-1 LIST OF TABLES TABLE 2-1. Address Modes ............................................ 2-18 2-2. Cross-Reference: Effective Addressing Mode, Given Operand Format and Type ................................. 2-20 2-3. Operand Resolution ....................................... 2-26 2-4a. Known Location of Operand & Instruction Follows SECTION .. 2-26 2-4b. Known Location of Operand & Instruction Follows ORG ...... 2-27 2-4c. Unknown Location of Operand & Instruction Follows SECTION or ORG ......................................... 2-27 2-4d. External Reference & Instruction Follows SECTION ......... 2-28 2-4e. External Reference & Instruction Follows ORG ............. 2-29 3-1. M68000 Family Assembler Directives ....................... 3-1 4-1. Standard Listing Format .................................. 4-3 6-1. Effective Addressing Modes for Compare Instructions ...... 6-6 iv ******************************************************************************** CHAPTER 1 GENERAL INFORMATION 1.1 SCOPE The intent of this publication is to provide sufficient information to develop M68000 Family assembly language programs, which may be run on MC68000- or MC68010-based systems. The information herein pertains to the elements of the assembler. Detailed information pertaining to the MC68000 microprocessor is provided in the MC68000 16-Bit Microprocessor User's Manual. Refer to the MC68010 16-Bit Virtual Memory Microprocessor product specification handbook for details on the MC68010. It is assumed that the designer has a complete understanding of the microprocessor architecture before attempting software development. Chapters 1 through 4 contain the basic features of the assembler needed by the beginning assembly language programmer. Chapter 4 also provides instructions to invoke the assembler. Advanced topics, such as macro operations, conditional assembly, and structured syntax, are described in Chapters 5 through 8. 1.2 INTRODUCTION The M68000 Family Resident Structured Assembler (referred to as the "assembler" throughout this manual) is used to translate M68000 family assembler source programs into MC68000/MC68010 machine language. The assembler executes under VERSAdos on the EXORmacs Development System, the VERSAmodule 01 or 02 Monoboard Microcomputer, the VMC 68/2 Microcomputer System, the VME/10 Microcomputer Development System, or VMEmodule Monoboard Microcomputer (MVME110). The assembler includes the following features: * Absolute/relocatable code generation * Complex expressions * Symbol table listing * Macros * Conditional assembly * Structured syntax * Cross-reference 1.3 M68000 FAMILY ASSEMBLY LANGUAGE The symbolic language used to code source programs for processing by the assembler is called assembly language. This language is composed of the following symbolic elements: a. Symbolic names or labels, which represent instruction, directive, and register mnemonics, as well as user-defined memory labels and macros. b. Numbers, which may be represented in binary, octal, decimal, or hexadecimal notation. c. Arithmetic and logical operators, which are employed in complex expressions. d. Special-purpose characters, which are used to denote certain operand syntax rules, macro functions, source line fields, and numeric bases. 1-1 ******************************************************************************** 1.3.1 Machine-Instruction Operation Codes Appendix A summarizes that part of the assembly language that provides mnemonic machine-instruction operation codes for the MC68000 and MC68010 machine instructions. 1.3.2 Directives The assembly language contains mnemonic directives which specify auxiliary actions to be performed by the assembler. Directives are not always translated to machine language. Assembler directives assist the programmer in controlling the assembler output, in defining data and symbols, and in allocating storage. 1.4 M68000 FAMILY RESIDENT STRUCTURED ASSEMBLER The assembler translates source statements written in the assembly language into relocatable object code, assigns storage locations to instructions and data, and performs auxiliary assembler actions designated by the programmer. Object modules produced by the assembler are compatible with the M68000 family linkage editor, referred to as the "linkage editor" or "linker". The assembler includes macro and conditional assembly capabilities, and implements certain "structured" programming control constructs. The assembler generates relocatable code which may then be linked into a memory image format. 1.4.1 Assembler Purposes The two basic purposes of the assembler are to: * Provide the programmer with the means to translate source statements into relocatable object code -- that is, to the format required by the linkage editor. * Provide a printed listing containing the source language input, assembler object code, and additional information (such as error codes, if any) useful to the programmer. 1.4.2 Assembler Processing Assembly is a two-pass process. During the first pass, the assembler develops a symbol table, associating user-defined labels with values and addresses. During the second pass, the translation from source language to machine language takes place, using the symbol table developed during pass 1. In pass 2, as each source line is processed in turn, the assembler generates appropriate object code and the assembly listing. 1-2 ******************************************************************************** 1.4.3 Microprocessor Types The assembler is designed for use with both MC68000 and MC68010 microprocessors. Its operation is functionally the same for either processor. In addition to supporting the MC68010's 28-bit addressing capability, the assembler provides three additional instruction mnemonics for use with the MC68010. To enable these additional mnemonics, however, the assembler must be so directed. This may be done either when the "command line" that invokes the assembler is entered, or in the first directive used in the source program. (Refer to paragraphs 4.1.2 and 3.5.2.10, respectively.) 1.5 RELOCATION AND LINKAGE "Relocation" refers to the process of binding a program to a set of memory locations at a time other than during the assembly process. For example, if subroutine "ABC" is to be used by many different programs, it is desirable to allow the subroutine to reside in any area of memory. One way of repositioning the subroutine in memory is to change the "ORG" directive operand field at the beginning of the subroutine, and then to re-assemble the routine. A disadvantage of this method is the expense of re-assembling ABC. An alternative to multiple assemblies is to assemble ABC once, producing an object module which contains enough information so that another program (the linkage editor) can easily assign a new set of memory locations to the module. This scheme offers the advantages that re-assembly is not required, the object module is substantially smaller than the source program, relocation is faster than re-assembly, and relocation can be handled by the linkage editor (rather than editing the source program and changing the ORG directive). In addition to program relocation, the linkage editor must also resolve inter- program references. For example, the other programs that are to use subroutine ABC must contain a jump-to-subroutine instruction to ABC. However, since ABC is not assembled at the same time as the calling program, the assembler cannot put the address of the subroutine into the operand field of the subroutine call. The linkage editor, however, will know where the calling program resides and, therefore, can resolve the reference to the call to ABC. This process of resolving inter-program references is called "linking". An example of linking two object modules is shown in Appendix D. Program sections provide the basis of the relocation and linking scheme. Each of these sections may also have a variable number of named common sections associated with it, with each common section having a unique name. These relocatable sections are passed on to the linkage editor, which concatenates all sections with the same number in the different modules to be linked. Each of the 16 relocatable sections may contain data and/or code; in addition, named common sections may be defined within any relocatable section. Absolute sections are unnumbered (and, therefore, unlimited in number); they are specified by the ORG directive. 1-3 ******************************************************************************** 1.6 LINKER RESTRICTIONS Before developing relocatable assembly language modules, the user should familiarize himself with the capabilities and restrictions of the linkage process, as outlined in the M68000 Family Linkage Editor User's Manual. It is important to keep in mind that the relocation features of the assembler are directly attributable to capabilities of the linkage editor, and that linkage environment can be controlled through assembler directives. If the assembly language object program is to be linked with a Pascal object program, the user should be aware of Pascal's requirements before allocation. The assembler will produce an object module compatible with the linkage editor. XDEF and XREF must be used to define entry points into the various modules and external symbols appearing in the module. 1.7 NOTATION Commands and other input/output (I/O) are presented in this manual in a modified Backus-Naur Form (BNF) syntax. Certain symbols in the syntax, where noted, are used in the real I/O; however, others are meta-symbols whose usage is restricted to the syntactic structure. These meta-symbols and their meanings are as follows: < > The angular brackets enclose a symbol, known as a syntactic variable, that is replaced in a command line by one of a class of symbols it represents. | This symbol indicates that a choice is to be made. One of several symbols, separated by this symbol, should be selected. [ ] Square brackets enclose a symbol that is optional. The enclosed symbol may occur zero or one time. [ ]... Square brackets followed by periods enclose a symbol that is optional/repetitive. The symbol may appear zero or more times. Operator entries are to be followed by a carriage return. 1.8 RELATED PUBLICATIONS The user should be familiar with the following Motorola publications: EXORmacs Development System Operations Manual (M68KMACS) MC68000 16-Bit Microprocessor User's Manual (MC68000UM) MC68010 16-Bit Virtual Memory Microprocessor Product Specification Handbook (ADI-942) M68000 Family Linkage Editor User's Manual (M68KLINK) M68000 Family Resident Pascal User's Manual (M68KPASC) VERSAdos Messages Reference Manual (M68KVMSG) VERSAdos System Facilities Reference Manual (M68KVSF) 1-4 ******************************************************************************** CHAPTER 2 SOURCE PROGRAM CODING 2.1 INTRODUCTION A source program is a sequence of source statements arranged in a logical way to perform a predetermined task. Each source statement occupies a line of printable text, where each line may be one of the following: a. Comment b. Executable instruction c. Assembler directive d. Macro invocation 2.2 COMMENTS Comments are strings, composed of any ASCII characters (refer to Appendix B), which are inserted into a program to identify or clarify the individual statements or program flow. Comments are included in the assembly listing but, otherwise, are ignored by the assembler. A comment may be inserted in one of two ways: a. At the beginning of a line, starting in column one, where an asterisk (*) is the first character in the line. The entire line is a comment, and an instruction or directive would not be recognized. b. Following the operation and operand fields of an assembler instruction or directive, where it is preceded by at least one space (see paragraph 2.4.4). Examples: * THIS ENTIRE LINE IS A COMMENT. BRA LAB2 THIS COMMENT FOLLOWS AN INSTRUCTION. 2.3 EXECUTABLE INSTRUCTION FORMAT Assembly language programs are translated by the assembler into relocatable object code. This object code may contain executable instructions, data structures, and relocation information. This translation process begins with symbolic assembly language source code, which employs reserved mnemonics, special symbols, and user-defined labels. M68000 family assembly language is line-oriented. 2-1 ******************************************************************************** 2.4 SOURCE LINE FORMAT Each source statement has an overall format that is some combination of the following four fields: a. label b. operation c. operand d. comment The statement lines in the source file must not be numbered. The assembler will prefix each line with a sequential number, up to four decimal digits. The format of each line of source code is described in the following paragraphs. 2.4.1 Label Field The label field is the first field in the source line. A label which begins in the first column of the line may be terminated by either a space or a colon. A label may be preceded by one or more spaces, provided it is then terminated by a colon. In neither case is the colon a part of the label. Labels are allowed on all instructions and assembler directives which define data structures. For such operations, the label is defined with a value equal to the location counter for the instruction or directive, including a designation for the program section in which the definition appears. Labels are required on the assembler directives which define symbol values (SET, EQU, REG). For these directives, the label is defined with a value (and for SET and EQU, a program section designation) corresponding to the expression in the operand field. Labels on MACRO definitions are saved as the mnemonic by which that macro is subsequently invoked. No memory address is associated with such labels. A label is also required on the IDNT directive. This label is passed on to the relocatable object module; it has no associated internal value. No other directives allow labels. Labels which are the only field in the source line will be defined equal to the current location counter value and program section. 2.4.2 Operation Field The operation field follows the label field and is separated from it by at least one space. Entries in the field would fall under one of the following categories: a. Instruction mnemonics - which correspond to the MC68000/MC68010 instruction set. b. Directive mnemonics - pseudo-operation codes for controlling the assembly process. c. Macro calls - invocations of previously-described macros. 2-2 ******************************************************************************** The size of the data field affected by an instruction is determined by the data size code. Some instructions and directives can operate on more than one data size. For these operations, the data size code must be specified or a default size of word (16-bit data) will be assumed. The size code need not be specified if only one data size is permitted by the operation. The data size code is specified by appending a period (.) to the operation field, followed by B, W, or L, where: B = Byte (8-bit data) W = Word (the default size; 16-bit data) L = Long word (32-bit data) The data size code is not permitted, however, when the instruction or directive does not have a data size attribute. Examples (legal): LEA 2(A0),A1 Long word size is assumed (.B, .W not allowed); this instruction loads effective address of first operand into A1. ADD.B ADDR,D0 This instruction adds byte whose address is ADDR to low order byte in D0. ADD D1,D2 This instruction adds low order word of D1 to low order word of D2. (W is the default size code.) ADD.L A3,D3 This instruction adds entire 32-bit (long word) contents of A3 to D3. Example (illegal): SUBA.B #5,A1 Illegal size specification (.B not allowed on SUBA). This instruction would have attempted to subtract the value 5 from the low order byte of A1; byte operations on address registers are not allowed. 2.4.3 Operand Field If present, the operand field follows the operation field and is separated from the operation field by at least one space. When two or more operand subfields appear within a statement, they must be separated by a comma but may not contain embedded spaces; e.g., D1, D2 is illegal. In an instruction like ' ADD D1,D2' the first subfield (D1) is generally applied to the second subfield (D2) and the results placed in the second subfield. Thus, the contents of D1 are added to the contents of D2 and the result is saved in register D2. In the instruction ' MOVE D1,D2' the first subfield (D1) is the sending field and the second subfield (D2) is the receiving field. In other words, for most two-operand instructions, the general format ' opcode source,destination' applies. 2.4.4 Comment Field The last field of a source statement is an optional comment field. This field is ignored by the assembler except for being included in the listing. The comment field is separated from the operand field (or the operation field, if there is no operand) by one or more spaces, and may consist of any ASCII characters. This field is important in documenting the operation of a program. 2-3 ******************************************************************************** 2.5 INSTRUCTION MNEMONICS The instruction operations described in paragraphs 2.5.1 through 2.5.12 are used by the assembler for both MC68000 and MC68010. Paragraphs 2.5.13 and 2.5.14, however, describe instructions which are valid only for the MC68010 microprocessor. 2.5.1 Arithmetic Operations The MC68000/MC68010 instruction set includes the operations of add, subtract, multiply, and divide. Add and subtract are available for all data operand sizes. Multiply and divide may be signed or unsigned. Operations on decimal data (BCD) include add, subtract, and negate. The general form is: . , Examples: ADD.W D1,D2 Adds low order word of D1 to low order word of D2. SUB.B #5,(A1) Subtracts value 5 from byte whose address is contained in A1. 2.5.2 MOVE Instruction The MOVE instruction is used to move data between registers and/or memory. The general form is: MOVE. , Examples: MOVE D1,D2 Moves low order word of D1 into low order word of D2. MOVE.L XYZ,DEF Moves long word addressed by XYZ into long word addressed by DEF. MOVE.W #'A',ABC Moves word with value of $4100 into word addressed by ABC. MOVE ADDR,A3 Moves word addressed by ADDR into low order word of A3. 2.5.3 Compare and Check Instructions The general formats of the compare and check instructions are: CMP. , CHK , 2-4 ******************************************************************************** where operand1 is compared to operand2 by the subtraction of operand1 from operand2 without altering operand1 or operand2. Condition codes resulting from the execution of the compare instruction are set so that a "less than" condition means that operand2 is less than operand1, and "greater than" means that operand2 is greater than operand1. The CHK instruction will cause a system trap if the register contents are less than zero or greater than the value specified by "bounds". Examples: CMP.L ADDR,D1 Compares long word at location ADDR with contents of D1, setting condition codes accordingly. CHK (A0),D3 Compares word whose address is in A0 with low order word of D3; if check fails (see text), a system trap is initiated. 2.5.4 Logical Operations Logical operations include AND, OR, EXCLUSIVE OR, NOT, and two logical test operations. These functions may be done between registers, between registers and memory, or with immediate source operands. The general form is: . , Example: AND D1,D2 Low order word of D2 receives logical 'and' of low order words in D1 and D2. The destination may also be the status register (SR). 2.5.5 Shift Operations Shift operations include arithmetic and logical shifts, as well as rotate and rotate with extend. All shift operations may be either fixed with the shift count in an immediate field or variable with the count in a register. Shifts in memory of a single bit position left or right may also be done. The general form is: . , Examples: LSL.W #5,D3 Performs a left, logical shift of low order word of D3 by 5 bits; .W is optional (default). ASR (A2) Performs a right, arithmetic shift of word whose address is contained in A2; since this is a memory operand, the shift is only 1 bit. ROXL.B D3,D2 Performs a left rotation with extend bit of low order byte of D2; shift count is contained in D3. 2-5 ******************************************************************************** 2.5.6 Bit Operations Bit operations allow test and modify combinations for single bits in either an 8-bit operand for memory destinations or a 32-bit operand for data register destinations. The bit number may be fixed or variable. The general form is: , Examples: BCLR #3,XYZ(A3) Clears bit number 3 in byte whose address is given by address in A3 plus displacement of XYZ. BCHG D1,D2 Tests a bit in D2, reflects its value in condition code Z, and then changes value of that bit; bit number is specified in D1. Under Mask3 of the MC68000 chip, the instructions BCLR, BSET, and BTST have 8-bit memory operands; under Mask2 they had 16-bit memory operands. To enable users who wrote programs under Mask2 -- using BCLR, BSET, and BTST instructions - to reassemble these programs under Mask3, the replacement instructions BCLRW, BSETW, and BTSTW are provided. These instructions align the destination operand at the next higher byte when bits 0-7 are accessed (thus functioning under Mask3 exactly as BCLR, BSET, and BTST functioned under Mask2). In making the change, replace only the instruction mnemonic; no change is required to the operand field. 2.5.7 Conditional Operations Condition codes can be used to set and clear data bytes. The general form is: Scc where "cc" may be one of the following condition codes: CC or HS GE LS PL CS or LO GT LT T EQ HI MI VC F LE NE VS Example: SNE (A5)+ If condition code "NE" (not equal) is true, then set byte whose address is in A5 to 1's; otherwise, set that byte to 0's; increment A5 by 1. 2.5.8 Branch Operations Branch operations include an unconditional branch, a branch to subroutine, and 14 conditional branch instructions. The general form is: . Examples: BRA TAG Unconditional branch to the address TAG. 2-6 ******************************************************************************** BSR SUBDO Branch to subroutine SUBDO. Bcc.S NEXT Short branch to NEXT on condition "cc", which may be one of the following condition codes (note that T and F are not valid condition codes for conditional branch): CC or HS GT LT VC CS or LO HI MI VS EQ LE NE GE LS PL All conditional branch instructions are PC-relative addressing only, and may be either one- or two-word instructions. The corresponding displacement ranges are: one-word -128...+127 bytes (8-bit displacement) two-word -32768...+32767 bytes (16-bit displacement) Forward references in branch instructions will use the longer format by default (OPT BRL). The default may be changed to the shorter format by specifying OPT BRS. The default extent may be overridden for a single branch operation by appending an "S" or "L" extent code to the instruction -- for example: BRA.L LAB A branch instruction with a byte displacement must not reference the statement which immediately follows it. This would result in an 8-bit displacement value of 0, which is recognized by the assembler as an error condition. Example (illegal): BEQ.S LAB1 LAB1 is the next memory word and, thus, generates LAB1 MOVE #1,D0 an error. 2.5.9 Jump Operations Jump operations include a jump to subroutine and an unconditional jump. The general form is: . Examples: JMP 4(A7) Unconditional jump to the location 4 bytes beyond the address in A7. JMP.L NEXT Long (absolute) jump to the address NEXT. JSR SUBDO Jump to subroutine SUBDO. Forward references to a label will use the long absolute address format by default (OPT FRL). The default may be changed to the shorter format by specifying OPT FRS. The default extent may be overridden on a single jump operation to a label by appending "S" or "L" as an extent code for the instruction. 2-7 ******************************************************************************** 2.5.10 DBcc Instruction This instruction is a looping primitive of three parameters: condition, data register, and label. The instruction first tests the condition to determine if the termination condition for the loop has been met and, if so, no operation is performed. If the termination condition is not true, the data register is decremented by one. If the result is -1, execution continues with the next instruction. If the result is not equal to -1, execution continues at the indicated location. Label must be within 16-bit displacement. The general format of the instruction is: DBcc ,