A first post here,

My name is Magnus Wedmark and have used EASy68K as a reference-bench for a FPGA-project I'm into as a hobby. EASy68K is a fantastic piece of software for lab-use and to learn the inner details in the 68k.

The project is about creating a minimal 68K-compatible IP-core for use in FPGA-projects. It is not an open project today, but it might be in the future if I get the complete 68k-opcode implemented. The reason to choose the 68K was that I just love it's assember opcode setup and I've done so since owning an Atari ST earlier! And also that the 68k-IP I've seen floating around seam to be BIG in terms of FPGA-resource needs.

The reason for me to post this here is to see if there are somebody interested in having a complete/partly-complete EASy68K-IP core? Wouldn't it be nice to have a hardware EASy68K-chip to run all programs on?

I'm using the original Xilinx Spartan-3 Starter Kit that includes a Spartan-3 200k FPGA. I read about the MECB project here in another discussion and I'm not sure if we collide?
I like to ask if anyone else have had the same idea as me or is it an orignal? Somebody interested? Projects already started?

Best Regards
Magnus

Hi, is your project still alive? I'm thinking of implementing 68k in FPGA.

Best regards,
Maja

Hello, Maja

Good to find another FPGA+68K hacker! What is you interest in such a project? EASy68K-HW or the core for use in other projects?

DISCLAIMER:
Remember that 68K is not your best first try at a core in VHDL/verilog. It was not developed this way. Both MIPS and ARM would probably be better more useful choices, thus x86 would be harder! But if you are, like me, not in it for simpleness or usefulness then the 68K is just a beautiful piece of nostalgic hardware. OK enough of disclaiming...

Depending on your definition of active, the project is at least not dead. It was however almost a year since I last visited it (2006-11). I check back here once in a while to see how EASy68K follow on and if there are more people interested in this HW spin-off. This far the reading of the thread has been high but the posting has been low and I'm not sure why!

Today this is not my main hobby-project but I'm still committed to finish it to get full or near full coverage of all 68k-op codes and then release it for others to play with. I have not decided if I'm going to aim for a drop-in replacement of a real MC68000 or just the op-code-execution unit... probably the ladder because cycle-accurate operation seem hard the way I chosen to implement it. There are still unanswered matters when it comes to the layout of my implementation. Is it really are possible to pull it off? I've chosen a path that make it Xilinx-only (Xilinx tools & hardware) to begin with but there is a way to broaden the image later on in the project if that would be someone's wish.

Todays status for it is approx:
- >30% of op-codes implemented, due to reusable parts maybe 50% done
- Handles B,W,L word sizes today
- 10 of 14 addressing-mode implemented
- When doing a quick overview it seem to resemble a <1Mhz 68K today
- It takes <10% of a 200K today

The first achievement will be to get a "Sierpinsky Triangle" program going that works in EASy68K, a simple fractal algorithm.

If someone is interested in more details than this, please mail me magnus(replace_this_with_at)wedmark.se and we'll take the off-topic details in a mail so we not clutter this list with even more details.

Of course I've already done a scan of which other open 68K-implementations there are out there floating around and only found two:

- SUSKA - a near complete Atari STE IP-core inc. a near complete 68K-core. The code is released now and then, it's big so you need to big FPGA to try it. Wolfgangs work is fantastic!
http://www.experiment-s.de/index.php?id=78&L=1

- There is a 68K core at opencores.org called - it is not finished but maybe it can be used as a start.. you can't find it when searching the site so just though I'd tip you off.
http://www.opencores.org/cvsweb.shtml/k68/

Anyone know of other 68K open-source IP's?

None if these cores have a goal similar to mine. The goal of my project is to get an absolute minimum core at the cost of performance which will be low in a first revision.

Depending on your goal, just for fun project or a school-work, maybe you have the possibility to learn from these.

OT warning:
And for an off-topic brief view of what I'm doing today visit:
http://wedmark.se

The thing called AE - Arcade Extender, is the hardware I've developed and are playing with. Together with my friends IP-core ULC (Ultimate Little Console) they form a gaming/demo platform. The specs and JAVA-simulator for ULC can be downloaded by following the descriptions from my webpage.

Right now I'm aiming for a C-compiler for it. The compiler will by built from scratch using the "COCO/R for C#" tools.

See ya!