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|Author:||lee [ Thu Apr 12, 2012 9:45 pm ]|
|Post subject:||Bcc.s timing|
As far as I can see short branches that aren't taken should only take 8 cycles and not the 12 cycles that Sim68K seems to think they should.
|Author:||clive [ Fri Apr 13, 2012 12:12 am ]|
BYTE displacement Not Taken 12, Taken 18
WORD displacement Not Taken 20, Taken 18
At least 68000UM 6th Edition
Edit: 68008 clocks
|Author:||lee [ Fri Apr 13, 2012 12:23 am ]|
Hmmmm. I'm getting my counts from table 8-9 in section 8.8 of the MC68000UM, ninth edition. Page 123 in the pdf I have. I'm probably forgetting to add the address mode count.
Whatever they should be they're not what Sim68K thinks they are.
|Author:||clive [ Fri Apr 13, 2012 12:53 am ]|
I'm digging through some other emulators and the're all over the map.
Cyclone thinks Taken is 10, BYTE Not Taken 8, WORD Not Taken 12
StarScream has all BYTE at 8, WORD at 12
EASy68K logic appears to match Cyclone
if (check_condition (condition))
inc_cyc ((inst & 0xff != 0) ? 8 : 12);
Ok my big numbers were from the 68008 table.
|Author:||profkelly [ Fri Apr 13, 2012 4:30 pm ]|
Interesting bug. The author's logic was sound. He was just missing a parenthesis. Corrected in Sim68K v5.12.3
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