EASy68K  
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PostPosted: Wed Apr 04, 2012 6:10 pm 
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Hi

ADDX.B -(A0),-(A0) accesses memory 3 times (read,read,write).

Neither the M68000PRM, the M68000_Users_Manual nor Google shed
any light on what the value of A0 should be for each of those accesses.

I can see that for the Easy68k simulator, if A0 = n, then all 3 accesses
are to n-1. This seems like the right thing to do but does anybody know
if that is the official specified behavior? Or maybe it is just the unspecified
behavior of some implementation. I don't have a real chip to try it on.

thanks
Aaron Boxer
Millogic
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PostPosted: Wed Apr 04, 2012 10:20 pm 
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Code:
    ADDX.B -(A0),-(A0)

Entry Conditions
X=0
A0=1022
1020 01 02

Easy68K Post
A0=1020
1020 02 02

IDE68K Post
A0=1020
1020 01 03

MC68EC040 Post
A0=1020
1020 03 02


The logical semantics here are
A0--
READ.B A0 ; @-1
A0--
READ.B A0 ; @-2
WRITE.B A0 ;@-2

The micro/nano-code is always going to operate on the source first, and then the destination second.

Under any interpretation EASy68K is busted. I don't have an 68000 with easy monitor access, I might be able to download something onto a 68EC020.

The 68EC040 is on a Motorola IDP board (M68EC0x0IDP) with 2MB of RAM, and a built in monitor (line assembler, debugger)
http://www.freescale.com/webapp/sps/sit ... 68EC0X0IDP

To confirm what EASy68K 5.9.0 is doing I ran another test, that illustrates all the read/write operations occur at A0-2
Code:
Entry Conditions
X=0
A0=1022
1020 11 33

Easy68K Post
A0=1020
1020 22 33


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PostPosted: Thu Apr 05, 2012 1:17 pm 
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EASy68K is broken. The correct values in memory should be
1020: 03 02

I'll add a post to the undocumented features.

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PostPosted: Thu Apr 05, 2012 4:29 pm 
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I am a little surprised that Easy68k is considered broken. I have designed
processors and I would have done it so that the following two instructions
generated the same result.

ADDX.B -(A0),-(A0)
ADDX.B -(A0),-(A1) ;where A0 = A1

It would be good to know what real silicon does but unfortunately I don't
have access to any.

Aaron Boxer
Millogic


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PostPosted: Thu Apr 05, 2012 5:03 pm 
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You have to remember that the 68000 is a 1979 era design with a clean, simple, linear, state machine using micro code, and nano code.

It's going to do things in a very simple, and straight forward interpretation, and it's not going to have pipeline hazards, and parallel operation.

One thing that will complicate the read order would be the prefetch of the next instruction word.

Designing a Verilog or VHDL implementation with no evaluation of an original silicon implementation is a tad dangerous. You need to dig up and old Mac, Atari ST, or Amiga. I occasionally see some 68K and CPU32 boards up on eBay.

I mentioned the arcade/amiga emulators earlier, as these have a far more rigid analysis (bus, cycle accurate), because games and demos rely on features on the processor that touch a lot of corner/boundary conditions in the device.

Emulations tend to cut corners in order to gain speed on the target platform. Quirky addressing modes, and undocumented behaviour, are all part of the fun. The 68K for example can ignore bits in the opcode fields that a 68020 won't.


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PostPosted: Thu Apr 05, 2012 5:10 pm 
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aboxer wrote:
It would be good to know what real silicon does but unfortunately I don't
have access to any.

I tested it on real silicon. The predecrement occurs once prior to fetching the source operand and again prior to accessing the destination.

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PostPosted: Thu Apr 05, 2012 5:27 pm 
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http://www.ebay.com/itm/Motorola-Busine ... 1854611375

http://www.ebay.com/itm/Motorola-MC6830 ... 5ae1c4751f

http://www.ebay.com/itm/MC68360-Kit-Emb ... 518dfd3441


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PostPosted: Thu Apr 05, 2012 6:40 pm 
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Thanks for the quick and thorough response! I think I will have to find
a real 68k board.

Aaron Boxer
Millogic


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PostPosted: Thu Apr 05, 2012 7:03 pm 
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See also the thread here which covers some other quirks. http://www.easy68k.com/EASy68Kforum/vie ... php?t=1092


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